Thin polished plates such as silicon wafers and the like are a very important part of modern technology. A wafer, for instance, may refer to a thin slice of semiconductor material used in the fabrication of integrated circuits and other devices. Other examples of thin polished plates may include magnetic disc substrates, gauge blocks and the like. While the technique described here refers mainly to wafers, it is to be understood that the technique also is applicable to other types of polished plates as well. The term wafer and the term thin polished plate may be used interchangeably in the present disclosure.
Fabricating semiconductor devices typically includes processing a substrate such as a semiconductor wafer using a number of semiconductor fabrication processes. Metrology processes are used at various steps during the semiconductor manufacturing process to monitor and control one or more semiconductor layer processes. One of the characteristics being monitored and controlled is the overlay error. An overlay measurement generally specifies how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it or how accurately a first pattern aligns with respect to a second pattern disposed on the same layer. The overlay error may be determined with an overlay target having structures formed on one or more layers of a work piece (e.g., semiconductor wafer). If the two layers or patterns are properly formed, then the structure on one layer or pattern tends to be aligned relative to the structure on the other layer or pattern. If the two layers or patterns are not properly formed, then the structure on one layer or pattern tends to be offset or misaligned relative to the structure on the other layer or pattern. Overlay error is the misalignment between any of the patterns used at different stages of the semiconductor fabrication processes.
When overlay errors are observed, an overlay measurement may be used to apply corrections to keep overlay errors within desired limits. For example, overlay measurements may be fed into an analysis routine that can calculate applicable scanner corrections to better align the process tools (e.g., a lithography tool) used in the fabrication process.
Overlay errors are typically corrected using fixed models such as linear models, high order correction (HOPC) models, intra-field high order correction (i-HOPC) models, Cascade models, Zernike models, Legendre models or the like. It is noted that linear and Cascade models are not sufficiently effective. HOPC and i-HOPC models, on the other hand, are not sufficiently robust. Therein lies a need for providing effective and robust overlay correction methods and systems.